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1 ? fn8209.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. ?2000 intersil inc., patents pending. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. preliminary x9523 laser diode control for fiber optic modules dual dcp, por, dual voltage monitors features ? two digitally controlled potentiometers (dcps) ?100 tap - 10k ? ?256 tap - 100k ? ?nonvolatile ?write protect function ? 2-wire industry standard serial interface ? power-on reset (por) circuitry ?programmable threshold voltage ?software selectable reset timeout ?manual reset ? two supplementary voltage monitors ?programmable threshold voltages ? single supply operation ?2.7v to 5.5v ? hot pluggable ? 20 pin packages ?xbga tm ?tssop description the x9523 combines two digitally controlled potenti- ometers (dcps), v1 / vcc power-on reset (por) cir- cuitry, qnd two programmable voltage monitor inputs with software and hardware indicators. all functions of the x9523 are accessed by an industry standard 2-wire serial interface. the dcps of the x9523 may be utilized to control the bias and modulation currents of the laser diode in a fiber optic module. the programmable por circuit may be used to ensure that v1 / vcc is stable before power is applied to the laser diode / module. the programmable voltage monitors may be used for monitoring various module alarm levels. the features of the x9523 are ideally suited to simpli- fying the design of fiber optic modules . the integra- tion of these functions into one package significantly reduces board area, cost and increases reliability of laser diode modules. block diagram data register command decode & control logic sda scl power-on / low voltage constat register protect logic threshold reset logic generation reset v2 vtrip v1 / vcc vtrip v3 + - 2 3 1 v1ro r h2 r w2 r l2 mr 8 wiper register r h1 r w1 r l1 counter v2ro wp v3ro 7 - bit nonvolatile memory nonvolatile memory wiper register counter 8 - bit 2 vtrip + - + - data sheet march 10, 2005
2 fn8209.0 march 10, 2005 detailed device description the x9523 combines two intersil digitally controlled potentiometer (dcp) device s, v1/vcc power-on reset control, v1/vcc low voltage reset control, and two sup- plementary voltage monitors in one package. these functions are suited to the control, support, and monitor- ing of various system parameters in fiber optic modules. the combination of the x952 3 fucntionality lowers sys- tem cost, increases reliability, and reduces board space requirements using intersil?s unique xbga? packaging. two high resolution dcps allow for the ?set-and-forget? adjustment of laser driver ic parameters such as laser diode bias and modulation currents. applying voltage to v cc activates the power-on reset circuit which allows the v1ro output to go high, until the supply the supply voltage stabilizes for a period of time (selectable via softwar e). the v1ro output then goes low. the low voltage reset circuitry allows the v1ro output to go high when v cc falls below the mini- mum v cc trip point. v1ro remains high until v cc returns to proper operating level. a manual reset (mr) input allows the user to externally trigger the v1ro out- put (high). two supplementary voltage monitor circuits continuously compare their inputs to individual trip voltages. if an input voltage exceeds it?s associated trip level, a hardware out- put (v3ro, v2ro) are allowed to go high. if the input voltage becomes lower than it?s associated trip level, the corresponding output is driven low. a corresponding binary representation of the two monitor circuit outputs (v2ro and v3ro) are also stored in latched, volatile (constat) register bits. the status of these two moni- tor outputs can be read out via the 2-wire serial port. intersil?s unique circuits allo w for all internal trip volt- ages to be individually programmed with high accu- racy. this gives the designer great flexibility in changing system parameters, either at the time of manufacture, or in the field. the device features a 2-wire interface and software protocol allowing operation on an i 2 c? compatible serial bus. pin configuration v2 r l2 nc 3 4 v1 / vcc scl nc nc r w1 r h1 7 8 v3 v ss 10 r l1 r h2 1 18 19 17 20 14 15 13 16 12 11 mr 6 r w2 2 sda 9 v3ro 5 wp v1ro v2ro not to scale xbga 20 pin tssop 2 3 4 a b c d e top view ? bumps down 1 r l2 r w2 r h2 v2 wp v3ro scl nc sda r l1 v2ro v1 / vcc v3 v1ro nc nc r h1 mr v ss r w1 x9523
3 fn8209.0 march 10, 2005 pin assignment pin xbga name function 1b3 r h2 connection to end of resistor array for (the 256 tap) dcp 2. 2a3 r w2 connection to terminal equivalent to the ?wiper? of a mechanical potentiometer for dcp 2. 3a4 r l2 connection to other end of resistor array for (the 256 tap) dcp 2. 4b4v3 v3 voltage monitor input. v3 is the input to a non-inverting voltage comparator circuit. when the v3 input is higher than the v trip3 threshold voltage, v3ro makes a transition to a high level. connect v3 to v ss when not used. 5c3v3ro v3 reset output. this open drain output makes a transition to a high level when v3 is greater than v trip3 and goes low when v3 is less than vtrip3. there is no delay circuitry on this pin. the v3ro pin requires the use of an external ?pull-up? resistor. 6d3mr manual reset. mr is a ttl level compatible input. pulling the mr pin active (high) initiates a reset cycle to the v1ro pin (v1/vcc reset output pin). v1ro will remain high for time t purst after mr has returned to it?s normally low state. the reset time can be selected using bits por1 and por0 in the constat register. the mr pin requires the use of an external ?pull-down? resistor. 7c4wp write protect control pin. wp pin is a ttl leve l compatible input. when held high, write pro- tection is enabled. in the enabled state, this pin prevents all nonvolatile ?write? operations. al- so, when the write protection is enabled, and th e device dcp write lock feature is active (i.e. the dcp write lock bit is ?1?), then no ?write? (volatile or nonvolatile) operations can be per- formedon the wiper position of any of the integrated digitally co ntrolled potentiometers (dcps). the wp pin uses an internal ?pull-down? resistor, thus if left floating the write protec- tion feature is disabled. 8d4scl serial clock. this is a ttl level compatible input pin used to control the serial bus timing for data input and output. 9e4sda serial data. sda is a bidirectional ttl level compatible pin used to transfer data into and out of the device. the sda pin input buffer is always active (not gated). this pin requires an external pull up resistor. 10 e1 vss ground. 11 e3 r l1 connection to other end of resistor for (the 100 tap) dcp 1. 12 e2 r w1 connection to terminal equivalent to the ?wiper? of a mechanical potentiometer for dcp 1. 13 d1 r h1 connection to end of resistor array for (the 100 tap) dcp 1. 17 b1 v2 v2 voltage monitor input. v2 is the input to a non-inverting voltage comparator circuit. when the v2 input is greater than the v trip2 threshold voltage, v2ro makes a transition to a high level. connect v2 to v ss when not used. 18 a1 v2ro v2 reset output. this open drain output makes a transition to a high level when v2 is great- er than v trip2 , and goes low when v2 is less than v trip2 . there is no power-up reset delay circuitry on this pin. the v2ro pin requires the use of an external ?pull-up? resistor. 19 b2 v1ro v1 / vcc reset output. this is an active high, open drain output which becomes active whenever v1 / vcc falls below v trip1 . v1ro becomes active on power-up and remains ac- tive for a time t purst after the power supply stabilizes (t purst can be changed by varying the por0 and por1 bits of the internal control register). the v1ro pin requires the use of an external ?pull-up? resistor. the v1ro pin can be forced active (high) using the manual reset (mr) input pin. 20 a2 v1 / vcc supply voltage. 14, 15, 16, c1, c2, d2 nc no connect. x9523
4 fn8209.0 march 10, 2005 principles of operation serial interface serial interface conventions the device supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive opera- tions. therefore, the x9523 operates as a slave in all applications. serial clock and data data states on the sda line can change only while scl is low. sda state changes while scl is high are reserved for indicating start and stop conditions. see figure 1.on power-up of the x9523, the sda pin is in the input mode. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda while scl is high. the device continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition has been met. see figure 2. serial stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop c ondition can only be issued after the transmitting devic e has released the bus. see figure 2. serial acknowledge an acknowledge (ack) is a software convention used to indicate a successful data transfer. the trans- mitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it receiv ed the eight bits of data. refer to figure 3. the device will respond wi th an acknowledge after recognition of a start condition if the correct device identifier bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subse- quent eight bit word. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. the device will ter- scl sda data stable data change data stable figure 1. valid data ch anges on the sda bus scl sda start stop figure 2. valid start and stop conditions x9523
5 fn8209.0 march 10, 2005 minate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to place the device into a known state. device internal addressing addressing protocol overview the user addressable internal components of the x9523 can be split up into two main parts: ?two digitally controlled potentiometers (dcps) ?control and status (constat) register depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 byte proto- col is used. all operations however must begin with the slave address byte being issued on the sda pin. the slave address selects the part of the x9523 to be addressed, and specifies if a read or write opera- tion is to be performed. it should be noted that in order to perform a write opera- tion to a dcp, the write enable latch (wel) bit must first be set (see ?wel: write enable latch (volatile)? on page 10.). slave address byte following a start condition, the master must output a slave address byte (refer to figure 4.). this byte con- sists of three parts: ?the device type identifier which consists of the most significant four bits of the slave address (sa7 - sa4). the device type identifier must always be set to 1010 in order to select the x9523. ?the next three bits (sa3 - sa1) are the internal device address bits. setting these bits to 111 internally selects the dcp structures in the x9523. the con- stat register may be selected using the internal device address 010. ?the least significant bit of the slave address (sa0) byte is the r/w bit. this bit defines the operation to be performed on the device being addressed (as defined in the bits sa3 - sa1). when the r/w bit is ?1?, then a read operation is selected. a ?0? selects a write operation (refer to figure 4.) nonvolatile write acknowledge polling after a nonvolatile write command sequence (for either the non volatile memory of a dcp (nvm), or the con- stat register) has been correctly issued (including the scl from master data output from transmitter data output from receiver 8 1 9 start acknowledge figure 3. acknowledge response from receiver scl from master sa6 sa7 sa5 sa3 sa2 sa1 sa0 device type identifier read / sa4 internal address (sa3 - sa1) internally addressed device 010 constat register 111 dcp all others reserved bit sa0 operation 0write 1 read r/w figure 4. slave address format 101 0 write address internal device x9523
6 fn8209.0 march 10, 2005 final stop condition), the x9523 initiates an internal high voltage write cycle. this cycle typically requires 5 ms. during this time, no further read or write commands can be issued to the device. write acknowledge polling is used to determine when this high voltage write cycle has been completed. to perform acknowledge polling, the master issues a start condition followed by a slave address byte. the slave address issued must contain a valid internal device address. the lsb of the slave address (r/w ) can be set to either 1 or 0 in this case. if the device is still busy with the high voltage cycle then no acknowledge will be returned. if the device has completed the write operation, an acknowledge will be returned and the host can then proceed with a read or write operation. (refer to figure 5.). digitally controlled potentiometers dcp functionality the x9523 includes two independent resistor arrays. these arrays respectively contain 99 and 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r hx and r lx inputs - where x = 1,2). at both ends of each array and between each resistor segment there is a cmos switch connected to the wiper (r w x ) output. within each individual array, only one switch may be turned on at any one time. these switches are controlled by the wiper counter register (wcr) (see figure 6). the wcr is a volatile register. on power-up of the x9523, wiper position data is auto- matically loaded into the wcr from its associated non volatile memory (nvm) register. the table below shows the initial values of the dcp wcr?s before the contents of the nvm is loaded into the wcr. ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes figure 5. acknowledge polling sequence decoder resistor array r hx fet switches r lx r wx 0 1 2 n wiper register counter non memory volatile (wcr) (nvm) ?wiper? figure 6. dcp internal structure dcp initial values before recall r 1 / 100 tap v l / tap = 0 r 2 / 256 tap v h / tap = 255 x9523
7 fn8209.0 march 10, 2005 the data in the wcr is then decoded to select and enable one of the respective fet switches. a ?make before break? sequence is used internally for the fet switches when the wiper is moved from one tap position to another. hot pluggability figure 7 shows a typical waveform that the x9523 might experience in a hot pluggable situation. on power-up, v1 / vcc applied to the x9523 may exhibit some amount of ringing, before it settles to the required value. the device is designed such that the wiper terminal (r wx ) is recalled to the correct position (as per the last stored in the dcp nvm), when the voltage applied to v1/vcc exceeds v trip1 for a time exceeding t purst (the power-on reset time, set in the constat register - see ?control and status register? on page 10.). therefore, if t trans is defined as the time taken for v1 / vcc to settle above v trip1 (figure 7): then the desired wiper terminal position is recalled by (a maximum) time: t trans + t purst . it should be noted that t trans is determined by system hot plug conditions. dcp operations in total there are three operations that can be performed on any internal dcp structure: ?dcp nonvolatile write ?dcp volatile write ?dcp read a nonvolatile write to a dcp will change the ?wiper position? by simultaneously writing new data to the associated wcr and nvm. therefore, the new ?wiper position? setting is recalled into the wcr after v1/vcc of the x9523 is powered down and then powered back up. a volatile write operation to a dcp however, changes the ?wiper position? by writing new data to the associated wcr only. the contents of the associated nvm register remains unchanged. therefore, when v1/vcc to the device is powered down then back up, the ?wiper position? reverts to that last position written to the dcp using a nonvolatile write operation. both volatile and nonvolatile write operations are executed using a three byte command sequence: (dcp) slave address byte, instruction byte, followed by a data byte (see figure 9) a dcp read operation allows the user to ?read out? the current ?wiper position? of the dcp, as stored in the associated wcr. this operation is executed using the random address read command sequence, consisting of the (dcp) slave address byte followed by an instruction byte and the slave address byte again (refer to figure 10.). instruction byte while the slave address byte is used to select the dcp devices, an instruction byte is used to determine which dcp is being addressed. the instruction byte (figure 8) is valid only when the device type identifier and the internal device address bits of the slave address are set to 1010111. in this case, the two least signific ant bit?s (i1 - i0) of the instruction byte are used to select the particular dcp (0 - 2). in the case of a write to any of the dcps (i.e. the lsb of the slave address is 0), the most significant bit of the instruction byte (i7), determines the write type (wt) performed. if wt is ?1?, then a nonvolatile write to the dcp occurs. in this case, the ?wiper position? of the dcp is changed by simultaneously writing new data to the associated figure 7. dcp power-up t v1/vcc v trip1 v1/vcc (max.) t purst maximum wiper recall time 0 t trans x9523
8 fn8209.0 march 10, 2005 wcr and nvm. therefore, the new ?wiper position? set- ting is recalled into the wcr after v1/vcc of the x9523 has been powered down then powered back up. if wt is ?0? then a dcp volatile write is performed. this operation changes the dcp ?wiper position? by writing new data to the associated wcr only. the contents of the associated nvm register remains unchanged. there- fore, when v1/vcc to the device is powered down then back up, the ?wiper position? reverts to that last written to the dcp using a nonvolatile write operation. dcp write operation a write to dcpx (x = 1,2) can be performed using the three byte command sequence shown in figure 9. in order to perform a write operation on a particular dcp, the write enable latch (wel) bit of the constat reg- ister must first be set (see ?wel: write enable latch (volatile)? on page 10.). the slave address byte 10101110 specifies that a write to a dcp is to be conducted. an acknowledge is returned by the x9523 after the slave address, if it has been received correctly. next, an instruction byte is issued on sda. bits p1 and p0 of the instruction byte determine which wcr is to be written, while the wt bit determines if the write is to be volatile or nonvolatile. if the instruction byte format is valid, another acknowledge is then returned by the x9523. following the instruction byte , a data byte is issued to the x9523 over sda. the data byte contents is latched into the wcr of the dcp on the first rising edge of the clock signal, after the lsb of the data byte (d0) has been issued on sda (see figure 29). the data byte determines the ?wiper position? (which fet switch of the dcp resistive array is switched on) of the dcp. the maximum value for the data byte depends upon which dcp is being addressed (see table below). using a data byte larger than the values specified above results in the ?wiper terminal? being set to the highest tap position. the ?wiper position? does not roll-over to the lowest tap position. for dcp2 (256 tap), the data byte maps one to one to the ?wiper position? of the dcp ?wiper terminal?. there- fore, the data byte 00001111 (15 10 ) corresponds to set- ting the ?wiper terminal? to tap position 15. similarly, the data byte 00011100 (28 10 ) corresponds to setting the ?wiper terminal? to tap position 28. the mapping of the data byte to ?wiper position? data for dcp1 (100 tap), is shown in ?appendix 1?. an ex ample of a simple c lan- guage function which ?translates? between the tap posi- tion (decimal) and the data byte (binary) for dcp1, is given in ?appendix 2?. wt ? description 0 select a volatile write operation to be performed on the dcp pointed to by bits p1 and p0 1 select a nonvolatile write operation to be per- formed on the dcp pointed to by bits p1 and p0 0 0 wt 0 0 0 p1 p0 write type dcp select ? this bit has no effect when a read operation is being performed. i5 i6 i7 i4 i3 i2 i1 i0 figure 8. instruction byte format s t a r t 10101110 a c k wt 0 0 0 0 0 p1 p0 a c k s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 slave address byte instruction byte data byte figure 9. dcp write command sequence p1- p0 dcpx # taps max. data byte 0 0 reserved 0 1 x = 1 100 refer to appendix 1 1 0 x = 2 256 ffh 1 1 reserved x9523
9 fn8209.0 march 10, 2005 it should be noted that all writes to any dcp of the x9523 are random in nature. therefore, the data byte of consecutive write operations to any dcp can differ by an arbitrary number of bits. also, setting the bits p1 = 1, p0 = 1 is a reserved sequence, and will result in no acknowledge after sending an instruction byte on sda. the factory default setting of all ?wiper position? settings is with 00h stored in the nvm of the dcps. this corre- sponds to having the ?wiper teminal? r wx (x = 1,2) at the ?lowest? tap position, therefore, the resistance between r wx and r lx is a minimum (essentially only the wiper resistance, r w ). dcp read operation a read of dcpx (x = 1,2) can be performed using the three byte random read command sequence shown in figure 10. the master issues the start condition and the slave address byte 10101110 which specifies that a ?dummy? write? is to be conducted. this ?dummy? write operation sets which dcp is to be read (in the preceding read operation). an acknowledge is returned by the x9523 after the slave address if received correctly. next, an instruction byte is issued on sda. bits p1-p0 of the instruction byte determine wh ich dcp ?wiper position? is to be read. in this case, the state of the wt bit is ?don?t care?. if the instruction byte format is valid, then another acknowledge is returned by the x9523. following this acknowledge, the master immediately issues another start condition and a valid slave address byte with the r/w bit set to 1. then the x9523 issues an acknowledge followed by data byte, and finally, the master issues a stop condition. the data byte read in this operation, corresponds to the ?wiper position? (value of the wcr) of the dcp pointed to by bits p1 and p0. slave address instruction byte a c k a c k s t a r t s t o p slave address data byte a c k s t a r t sda bus signals from the slave signals from the master figure 10. dcp read sequence ?dummy? write read operation 101 111 0 0 00 00 0 w t p 1 p 0 101 111 1 0 write operation - msb lsb dcpx x = 1 x = 2 ?-? = don?t care s t a r t s t o p slave address address byte data byte a c k a c k a c k sda bus signals from the slave signals from the master figure 11. eeprom byte write sequence internal device address 1 01 0 0 0 0 0 write operation x9523
10 fn8209.0 march 10, 2005 it should be noted that when reading out the data byte for dcp1 (100 tap), the upper most significant bit is an ?unknown?. for dcp2 (256 tap) however, all bits of the data byte are relevant (see figure 10). control and status register the control and status (constat) register pro- vides the user with a mechanism for changing and reading the status of various parameters of the x9523 (see figure 12). the constat register is a combination of both volatile and nonvolatile bits. the nonvolatile bits of the con- stat register retain their stored values even when v1/vcc is powered down, then powered back up. the volatile bits however, will always power-up to a known logic state ?0? (irrespective of their value at power-down). a detailed description of the function of each of the con- stat register bits follows: wel: write enable latch (volatile) the wel bit controls the write enable status of the entire x9523 device. this bit must first be enabled before any write operation (to dcps, or the constat regis- ter). if the wel bit is not first enabled, then any pro- ceeding (volatile or nonvolatile) write operation to dcps or the constat register, is aborted and no acknowl- edge is issued after a data byte. the wel bit is a volatile latch that powers up in the dis- abled, low (0) state. the wel bit is enabled / set by writing 00000010 to the constat register. once enabled, the wel bit remains set to ?1? until either it is reset to ?0? (by writing 00000000 to the constat regis- ter) or until the x9523 powers down, and then up again. writes to the wel bit do not cause an internal high volt- age write cycle. therefore, the device is ready for another operation immediately after a stop condition is executed in the constat write command sequence (see figure 13). rwel: register write en able latch (volatile) the rwel bit controls the (constat) register write enable status of the x9523. therefore, in order to write to any of the bits of the constat register (except wel), the rwel bit must first be set to ?1?. the rwel bit is a volatile bit that powers up in the disabled, low (?0?) state. it must be noted that the rwel bit can only be set, once the wel bit has first been enabled (see "constat register write operation"). the rwel bit will reset itself to the default ?0? state, in one of two cases: ?after a successful write operation to any bits of the constat register has been completed (see figure 13). ?when the x9523 is powered down. dwlk: dcp write lock bit - (nonvolatile) the dcp write lock bit (dwlk) is used to inhibit a dcp write operation (changing the ?wiper position?). when the dcp write lock bi t of the constat register is set to ?1?, then the ?wi per position? of the dcps can- not be changed - i.e. dcp wr ite operations cannot be conducted: the factory default setting for this bit is dwlk = 0. important note: if the write protect (wp) pin of the x9523 is active (high), then nonvolatile write operations to the dcps are inhibited, irrespective of the dcp write lock bit setting (see "wp: write protection pin"). bit(s) description por1 power-on reset bit v2os v2 output status flag v1os v1 output status flag cs4 always set to ?0? (reserved) dwlk sets the dcp write lock rwel register write enable latch bit wel write enable latch bit por0 power-on reset bit por1 wel por0 cs5 cs6 cs7 cs4 cs3 cs2 cs1 cs0 v3os v2os dwlk 0 rwel figure 12. constat register format nv nv nv note: bits labelled nv are nonvolatile (see ?control and status register?). dwlk dcp write operation permissible 0 yes (default) 1no x9523
11 fn8209.0 march 10, 2005 por1, por0: power-on reset bits - (nonvolatile) applying voltage to v cc activates the power-on reset circuit which holds v1ro output high, until the supply voltage stabilizes above the v trip1 threshold for a period of time, t purst (see figure 25). the power-on reset bits, por1 and por0 of the constat register determine the tpurst delay time of the power-on reset circuitry (see "voltage moni- toring functions"). these bits of the constat register are nonvolatile, and therefore power-up to the last written state. the nominal power-on reset delay time can be selected from the following table, by writing the appropriate bits to the constat register: the default for these bits are por1 = 0, por0 = 1. v2os, v3os: voltage monitor status bits (volatile) bits v2os and v3os of the constat register are latched, volatile flag bits which indicate the status of the voltage monitor reset output pins v2ro and v3ro. at power-up the vxos (x = 2,3) bits default to the value ?0?. these bits can be set to a ?1? by writing the appropri- ate value to the constat register. to provide consis- tency between the vxro and vxos however, the status of the vxos bits can only be set to a ?1? when the corre- sponding vxro output is high. once the vxos bits have be en set to ?1?, they will be reset to ?0? if: ?the device is powered down, then back up, ?the corresponding vxro output becomes low. constat register write operation the constat register is accessed using the slave address set to 1010010 (refer to figure 4.). following the slave address byte, access to the constat regis- ter requires an address byte which must be set to ffh. only one data byte is allo wed to be written for each constat register write operation. the user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that st ores the dwlk, por1 and por0 bits. the x9523 will not acknowledge any data bytes written after the first byte is entered (refer to figure 13.). when writing to the constat register, the bit cs4 must always be set to ?0?. writing a ?1? to bit cs4 of the con- stat register is a reserved operation. prior to writing to the constat register, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps ?write a 02h to the constat register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation preceded by a start and ended with a stop). ?write a 06h to the constat register to set the reg- ister write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation preceded by a start and ended with a stop). por1 por0 power-on reset delay (t puv1ro ) 0 0 50ms 0 1 100ms (default) 1 0 200ms 1 1 300ms s t a r t 1 010010r/w a c k 11111 1 11 a c k scl sda s t o p a c k cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 slave address byte address byte constat register data in figure 13. constat register write command sequence x9523
12 fn8209.0 march 10, 2005 ?write a one byte value to the constat register that has all the bits set to the desired state. the constat register can be represented as qxyst01r in binary, where xy are the voltage monitor output status (v2os and v3os) bits, t is the dcp write lock (dwlk) bit, and qr are the power-on reset delay time (t puv1ro ) control bits (por1 - por0). this operation is proceeded by a start and ended with a stop bit. since this is a nonvolatile write cycle, it will typically take 5ms to comple te. the rwel bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. if bit 2 is set to ?1? in this third step (qxys t11r) then the rw el bit is set, but the v2os, v3os, por1, por0, and dwlk bits remain unchanged. writing a second byte to the control regis- ter is not allowed. doing so aborts the write operation and the x9523 does not return an acknowledge. for example, a sequence of writes to the device con- stat register consisting of [02h, 06h, 02h] will reset all of the nonvolatile bits in the constat register to ?0?. it should be noted that a write to any nonvolatile bit of constat register will be igno red if the write protect pin of the x9523 is active (high) (see "wp: write protection pin"). constat register read operation the contents of the constat register can be read at any time by performing a random read (see figure 14). using the slave address byte set to 10100101, and an address byte of ffh. only one byte is read by each reg- ister read operation. the x9523 resets itself after the first byte is read. the master should supply a stop condition to be consistent with the bus protocol. after setting the wel and / or the rwel bit(s) to a ?1?, a constat register read oper ation may occur, without interrupting a proceeding co nstat register write operation. when performing a read operation on the constat registerm, bit cs4 will always return a ?0? value. data protection there are a number of levels of data protection fea- tures designed into the x9523. any write to the device first requires setting of the wel bit in the constat register. a write to the constat register itself, further requires the setting of the rwel bit. dcp write lock protection of the device en ables the user to inhibit writes to all the dcps. one fu rther level of data protec- tion in the x9523, is incorporated in the form of the write protection pin. x9522 write permission status figure 14. constat register read command sequence 0 slave address address byte a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master 0 1 0 0 1 0 11 0 1 0 0 1 0 write operation ?dummy? write read operation cs7 ? cs0 dwlk (dcp write lock bit status) wp (write protect pin status) dcp volatile write permitted dcp nonvolatile write permitted write to constat register permitted volatile bits nonvolatile bits 1 1 no no no no 01yesnonono 1 0 no no yes yes 0 0 yes yes yes yes x9523
13 fn8209.0 march 10, 2005 wp: write protection pin when the write protection (wp) pin is active (high), it disables nonvolatile write operations to the x9523. the table below (x9523 write permission status) sum- marizes the effect of the wp pin (and dcp write lock), on the write permission status of the device. additional data protection features in addition to the preceding features, the x9523 also incorporates the following data protection functionality: ?the proper clock count and data bit sequence is required prior to the stop bit in order to start a nonvol- atile write cycle. voltage monitoring functions v1 / vcc monitoring the x9523 monitors the supply voltage and drives the v1ro output high (using an external ?pull up? resistor) if v1/vcc is lower than v trip1 threshold. the v1ro output will remain high until v1/vcc exceeds v trip1 for a minimum time of t purst . after this time, the v1ro pin is driven to a low state. see figure 25. for the power-on/low voltage reset function of the x9523, the v1ro output may be driven high down to a v1/vcc of 1v (v rvalid ). see figure 25. another feature of the x9523, is that the value of t purst may be selected in software via the constat register (see ?por1, por0: power-on reset bits - (nonvolatile)? on page 11.). it is recommended to stop communication to the device while while v1ro is high. also, setting the manual reset (mr) pin high overrides the power-on/low voltage circuitry and forces the v1ro output pin high (see "manual reset"). manual reset the v1ro output can be forced high externally using the manual reset (mr) input. mr is a de-bounced, ttl compatible input, and so it may be operated by connect- ing a push-button directly from v1/vcc to the mr pin. v1ro remains high for time t purst after mr has returned to its low state (s ee figure 15). an external ?pull down? resistor is required to hold this pin (nor- mally) low. v2 monitoring the x9523 asserts the v2ro output high if the volt- age v2 exceeds the corresponding v trip2 threshold (see figure 16). the bit v2os in the constat regis- ter is then set to a ?0? (assuming that it has been set to ?1? after system initilization). the v2ro output may remain active high with v cc down to 1v. v3 monitoring the x9523 asserts the v3ro output high if the volt- age v3 exceeds the corresponding v trip3 threshold (see figure 16). the bit v3os in the constat regis- ter is then set to a ?0? (assuming that it has been set to ?1? after system initilization). the v3ro output may remain active high with v cc down to 1v. mr v1ro v1 / vcc 0 volts 0 volts t purst figure 15. manual reset response 0 volts v trip1 figure 16. voltage monitor response vx vxro 0v 0v v tripx (x = 2,3) 0 volts v trip1 v1 / vcc x9523
14 fn8209.0 march 10, 2005 v tripx thresholds (x = 1,2,3) the x9523 is shipped with pre-programmed threshold (v tripx ) voltages. in applications where the required thresholds are different from the default values, or if a higher precision/tolerance is required, the x9523 trip points may be adjusted by the user, using the steps detailed below. setting a v tripx voltage (x = 1,2,3) there are two procedures used to set the threshold voltages (v tripx ), depending if the threshold voltage to be stored is higher or lower than the present value. for example, if the present v tripx is 2.9 v and the new v tripx is 3.2 v, the new voltage can be stored directly into the v tripx cell. if however, the new setting is to be lower than the presen t setting, then it is neces- sary to ?reset? the v tripx voltage before setting the new value. setting a higher v tripx voltage (x = 1,2,3) to set a v tripx threshold to a new voltage which is higher than the present thres hold, the user must apply the desired v tripx threshold voltage to the corre- sponding input pin (v1/vcc, v2 or v3). then, a pro- gramming voltage (vp) must be applied to the wp pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h, followed by the byte address 01h for v trip1 , 09h for v trip2 , and 0dh for v trip3 , and a 00h data byte in order to pro- gram v tripx . the stop bit following a valid write operation initiates the programming sequence. pin wp must then be brought low to complete the operation (see figure 18). the user does not have to set the wel bit in the constat register before performing this write sequence. 01234567 scl sda a0h 01234567 wp v p 01234567 v tripx v2, v3 01h ? sets v trip1 figure 17. setting v tripx to a higher level (x = 1,2,3). 09h ? sets v trip2 0dh ? sets v trip3 data byte ? v1 / vcc 00h s t a r t ? ? all others reserved. sda a0h ? 01234567 scl 01234567 wp v p 01234567 figure 18. resetting the v tripx level 03h ? resets vtrip1 0bh ? resets vtrip2 0fh ? resets vtrip3 data byte 00h ? s t a r t ? all others reserved. x9523
15 fn8209.0 march 10, 2005 setting a lower v tripx voltage (x = 1,2,3). in order to set v tripx to a lower voltage than the present value, then v tripx must first be ?reset? accord- ing to the procedure described below. once v tripx has been ?reset?, then v tripx can be set to the desired voltage using the procedure described in ?setting a higher v tripx voltage?. resetting the v tripx voltage (x = 1,2,3). to reset a v tripx voltage, apply the programming volt- age (vp) to the wp pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h followed by the byte address 03h for v trip1 , 0bh for v trip2 , and 0fh for v trip3 , followed by 00h for the data byte in order to reset v tripx . the stop bit following a valid wr ite operation initiates the programming sequence. pin wp must then be brought low to complete the operation (see figure 18).the user does not have to set the wel bit in the con- stat register before perfor ming this write sequence. after being reset, the value of v tripx becomes a nomi- nal value of 1.7v. v tripx accuracy (x = 1,2,3). the accuracy with which the v tripx thresholds are set, can be controlled using the iterative process shown in figure 19. if the desired threshold is less that the present threshold voltage, then it must first be ?reset? (see "resetting the vtripx voltage (x = 1,2,3)." ) . the desired threshold voltage is then applied to the appropriate input pin (v1/vcc, v2 or v3) and the proce- dure described in section ?setting a higher v tripx voltage? must be followed. once the desired v tripx threshold has been set, the error between the desired and (new) actual set threshold can be determined. this is achieved by applying v1/vcc to the device, and then applying a test voltage higher than the desired threshold voltage, to the input pin of the voltage monitor circuit whose v tripx was programmed. for example, if v trip2 was set to a desired level of 3.0v, then a test voltage of 3.4 v may be applied to the voltage monitor input pin v2. in the case of setting of v trip1 then only v1/vcc need be applied. in all cases, care should be taken not to exceed the maximum input voltage limits. after applying the test voltage to the voltage monitor input pin, the test voltage can be decreased (either in dis- crete steps, or continuously) until the output of the volt- age monitor circuit changes state. at this point, the error between the actua measured, and desired threshold lev- els is calculated. for example, the desired threshold for v trip2 is set to 3.0v, and a test voltage of 3.4v was applied to the input pin v2 (after applying power to v1/vcc). the input volt- age is decreased, and found to trip the associated output level of pin v2ro from a low to a high, when v2 reaches 3.09v. from this, it can be calculated that the programming error is 3.09 - 3.0 = 0.09v. if the error between the desired and measured v tripx is less than the maximum desired error, then the program- ming process may be terminated. if however, the error is greater than the maximum desired error, then another iteration of the v tripx programming sequence can be performed (using the calculated error) in order to further increase the accuracy of the threshold voltage. if the calculated error is greater than zero, then the v tripx must first be ?reset?, and then programmed to the a value equal to the previously set v tripx minus the cal- culated error. if it is the case that the error is less than zero, then the v tripx must be programmed to a value equal to the previously set v tripx plus the absolute value of the calculated error. continuing the previous example, we see that the calcu- lated error was 0.09v. since this is greater than zero, we must first ?reset? the v trip2 threshold, then apply a volt- age equal to the last previously programmed voltage, minus the last previously calculated error. therefore, we must apply v trip2 = 2.91 v to pin v2 and execute the programming sequence (see "setting a higher vtripx voltage (x = 1,2,3)" ) . using this process, the desired accuracy for a particu- lar v tripx threshold may be attained using a succes- sive number of iterations. x9523
16 fn8209.0 march 10, 2005 v tripx programming apply vcc & voltage decrease vx switches? actual v tripx - desired v tripx done execute sequence v tripx reset set vx = desired v tripx execute sequence set higher v tripx new vx applied = old vx applied + | error | execute sequence reset v tripx new vx applied = old vx applied - | error | error < mde ? | error | < | mde | yes no error >mde + no yes figure 19. v tripx setting / reset sequence (x = 1,2,3) > desired v tripx to vx desired v tripx < present value? note: x = 1,2,3. let: mde = maximum desired error output acceptable error range mde + mde ? error = actual ? desired = error desired value x9523
17 fn8209.0 march 10, 2005 absolute maximum ratings recommended operating conditions note: stresses above those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended peri- ods may affect device reliability figure 20. equivalent a.c. circuit figure 21. dcp spice macromodel parameter min. max. units temperature under bias -65 +135 c storage temperature -65 +150 c voltage on wp pin (with respect to vss) -1.0 +15 v voltage on other pins (with respect to vss) -1.0 +7 v | voltage on r hx - voltage on r lx | (x = 0,1,2. referenced to vss ) v1/vcc v d.c. output current (sda,v1ro,v2ro,v3ro) 0 5ma lead temperature (soldering, 10 seconds) 300 c supply voltage limits (applied v1/vcc voltage, referenced to vss) 2.7 5.5 v temperature min. max. units commercial 070 c industrial -40 +85 c v1 / vcc = 5v v2ro 100pf sda 2300 ? v3ro v1ro c h c l r wx 10pf 10pf r hx r lx r total c w 25pf r w (x=0,1,2) x9523
18 fn8209.0 march 10, 2005 timing diagrams figure 22. bus timing figure 23. wp pin timing figure 24. write cycle timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r t hd:wp scl sda in wp t su:wp clk 1 clk 9 start scl sda t wc 8th bit of last byte ack stop condition start condition x9523
19 fn8209.0 march 10, 2005 figure 25. power-up and power-down timing figure 26. manual reset timing diagram figure 27. v2, v3 timing diagram v1/vcc t purst t r t f 0 volts v trip1 v1ro t rpd 0 volts t purst mr 0 volts 0 volts mr v1ro t purst t mrd 0 volts v1 / vcc v1/vcc v trip1 t mrpw vx t rx t fx v tripx v rvalid vxro t rpdx 0 volts note : x = 2,3. 0 volts 0 volts t rpdx t rpdx t rpdx v trip1 v1/vcc x9523
20 fn8209.0 march 10, 2005 figure 28. v tripx programming timing diagram (x = 1,2,3). figure 29. dcp ?wiper position? timing wp t vps v p t vpo scl sda t wc t tsu t thd v vcc, v2, v3 v tripx 00h t vph note : v1/vcc must be greater than v2, v3 when programming. s t a r t 10101110 a c k wt 0 0 0 0 0 p1 p0 a c k s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 slave address byte instruction byte data byte scl sda time rwx (x = 0,1,2) t wr r wx(n + 1) r wx(n - 1) r wx(n) n = tap position x9523
21 fn8209.0 march 10, 2005 d.c. operating characteristics notes: 1. the device enters the active state after any start, an d remains active until: 9 clock cycles later if the device sele ct bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. notes: 2. the device goes into standby: 200ns after any stop , except those that initiate a high voltage write cycle; t wc after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave addre ss byte. notes: 3. current through external pull up resistor not included. notes: 4. v in = voltage applied to input pin. notes: 5. v out = voltage applied to output pin. notes: 6. see ?ordering information? on page 30. notes: 7. v il min. and v ih max. are for reference only and are not tested symbol parameter min typ max unit test conditions / notes i cc1 (1) current into v cc pin (x9523: active) read memory array (3) write nonvolatile memory 0.4 1.5 ma f scl = 400khz i cc2 (2) current into v cc pin (x9523:standby) with 2-wire bus activity (3) no 2-wire bus activity 50 50 a v sda = v cc mr = vss wp = vss or open/floating v scl = v cc (when no bus activity else f scl = 400khz) i li input leakage current (scl, sda, mr) 0.1 10 a v in (4) = gnd to v cc. input leakage current (wp) 10 a i ai analog input leakage 1 10 a v in = v ss to v cc with all other an- alog pins floating i lo output leakage current (sda, v1ro, v2ro, v3ro) 0.1 10 a v out (5) = gnd to v cc. x9523 is in standby (2) v trip1pr v trip1 programming range 2.75 4.70 v v tripxpr v tripx programming range (x = 2,3) 1.8 4.70 v v trip1 (6) pre - programmed v trip1 threshold 2.85 4.55 3.0 4.7 3.05 4.75 v factory shipped default option a factory shipped default option b v trip2 (6) pre - programmed v trip2 threshold 1.65 2.85 1.8 3.0 1.85 3.05 v factory shipped default option a factory shipped default option b v trip3 (6) pre - programmed v trip3 threshold 1.65 2.85 1.8 3.0 1.85 3.05 v factory shipped default option a factory shipped default option b i vx v2 input leakage current v3 input leakage current 1 1 a v sda = v scl = v cc others=gnd or v cc v il (7) input low voltage (scl, sda, wp, mr) -0.5 0.8 v v ih (7) input high voltage (scl,sda, wp, mr) 2.0 v cc +0.5 v v olx v1ro, v2ro, v3ro, sda output low voltage 0.4 v i sink = 2.0ma x9523
22 fn8209.0 march 10, 2005 a.c. characteristics (see fi gure 22, figure 23, figure 24) a.c. test conditions nonvolatile write cycle timing capacitance (t a = 25c, f = 1.0 mhz, v cc = 5v) notes: 1. typical values are for t a = 25c and v cc = 5.0v notes: 2. cb = total capacitance of one bus line in pf. notes: 3. over recommended operating conditions, unless ot herwise specified notes: 4. t wc is the time from a valid stop condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless ac knowledge polling is used. notes: 5. this parameter is not 100% tested. symbol parameter 400khz min max units f scl scl clock frequency 0 400 khz t in (5) pulse width suppression time at inputs 50 ns t aa (5) scl low to sda data out valid 0.1 0.9 s t buf (5) time the bus free before st art of new transmission 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh (5) data output hold time 50 ns t r (5) sda and scl rise time 20 +.1cb (2) 300 ns t f (5) sda and scl fall time 20 +.1cb (2) 300 ns t su:wp wp setup time 0.6 s t hd:wp wp hold time 0 s cb (5) capacitive load for each bus line 400 pf input pulse levels 0.1v cc to 0.9v cc input rise and fall times 10ns input and output timing levels 0.5v cc output load see figure 20 symbol parameter min. typ.(1) max. units t wc (4) nonvolatile write cycle time 5 10 ms symbol parameter max units test conditions c out (5) output capacitance (sda, v1ro, v2ro, v3ro) 8 pf v out = 0v c in (5) input capacitance (scl, wp, mr) 6 pf v in = 0v x9523
23 fn8209.0 march 10, 2005 potentiometer characteristics notes: 1. power rating between the wiper terminal r wx(n) and the end terminals r hx or r lx - for any tap position n, (x = 0,1,2). notes: 2. absolute linearity is utilized to determine actual wiper resistance vers us, expected resistance = (r wx(n) (actual) - r wx(n) (expected)) = 1 ml maximum (x = 0,1,2). notes: 3. relative linearity is a measure of the error in step size between taps = r wx(n+1) - [r wx(n) + ml] = 1 ml (x = 0,1,2) notes: 4. 1 ml = minimum increment = r tot / (number of taps in dcp - 1). notes: 5. typical values are for t a = 25c and nominal supply voltage. notes: 6. this parameter is periodically sampled and not 100% tested. symbol parameter limits test conditions/notes min. typ. max. units r tol end to end resistance tolerance -20 +20 % v rhx r h terminal voltage (x = 0,1,2) vss v cc v v rlx r l terminal voltage (x = 0,1,2) vss v cc v p r power rating (1)(6) 10 mw r total = 10k ? ( dcp0, dcp1) 5mw r total = 100k ? ( dcp2) r w dcp wiper resistance 200 400 ? i w = 1ma, v cc = 5v, v rhx = vcc, v rlx = vss (x = 0,1,2). 400 1200 ? i w = 1ma, v cc = 2.7v, v rhx = vcc, v rlx = vss (x = 0,1,2) i w wiper current (6) 4.4 ma noise mv/ sqt(hz) r total = 10k ? ( dcp0, dcp1) mv/ sqt(hz) r total = 100k ? ( dcp2) absolute linearity (2) -1 +1 mi (4) r w(n)(actual) - r w(n)(expected) relative linearity (3) -1 +1 mi (4) r w(n + 1) - [r w(n) + mi ] r total temperature coefficient 300 ppm/c r total = 10k ? ( dcp0, dcp1) 300 ppm/c r total = 100k ? ( dcp2) c h /c l /c w potentiometer capacitances 10/10/25 pf see figure 21. t wr wiper response time (6) 200 s see figure 29. x9523
24 fn8209.0 march 10, 2005 v tripx (x = 1,2,3) programming parameters (see figure 28) notes: the above parameters are not 100% tested. v1ro, v2ro, v3ro output timing. (see figure 25, figure 26, figure 27) notes: 1. see figure 26 for timing diagram. notes: 2. see figure 20 for equivalent load. notes: 3. this parameter describes the lo west possible v1/vcc level for which the ou tputs v1ro, v2ro, and v3ro will be correct with respect to their inputs (v1/vcc, v2, v3). notes: 4. from mr rising edge crossing v ih , to v1ro rising edge crossing v oh . notes: 5. the above parameters are not 100% tested. parameter description min typ max units t vps v tripx program enable voltage setup time 10 s t vph v tripx program enable voltage hold time 10 s t tsu v tripx setup time 10 s t thd v tripx hold (stable) time 10 s t vpo v tripx program enable voltage off time (between successive adjustments) 1ms t wc v tripx write cycle time 510 ms v p programming voltage 10 15 v v ta v tripx program voltage accuracy (programmed at 25 o c.) -100 +100 mv v tv v trip program variation after programming (-40 - 85 o c). (programmed at 25 o c.) -25 +10 +25 mv symbol description condition min. typ. max. units t purst (5) power-on reset delay time por1 = 0, por0 = 0 25 50 75 ms por1 = 0, por0 = 1 50 100 150 ms por1 = 1, por0 = 0 100 200 300 ms por1 = 1, por0 = 1 150 300 450 ms t mrd (26)(2)(5) mr to v1ro propagation delay see (1)(2)(4) 5 s t mrdpw (5) mr pulse width 500 ns t rpdx (5) v vcc, v2, v3 to v1ro, v2ro, v3ro propagation delay (respectively) 20 s t fx (5) v1/vcc, v2, v3 fall time 20 mv/ s t rx (5) v1/vcc, v2, v3 rise time 20 mv/ s v rvalid (5) v1/vcc for v1ro, v2ro, v3ro valid (3) . 1v x9523
25 fn8209.0 march 10, 2005 appendix 1 dcp1 (100 tap) tap position to data byte translation table tap position data byte decimal binary 0 0 0000 0000 1 1 0000 0001 . . . . . . 23 23 0001 0111 24 24 0001 1000 25 56 0011 1000 26 55 0011 0111 . . . . . . 48 33 0010 0001 49 32 0010 0000 50 64 0100 0000 51 65 0100 0001 . . . . . . 73 87 0101 0111 74 88 0101 1000 75 120 0111 1000 76 119 0111 0111 . . . . . . 98 97 0110 0001 99 96 0110 0000 x9523
26 fn8209.0 march 10, 2005 appendix 2 dcp1 (100 tap) tap position to data byte translation algorithm example. (example 1) unsigned dcp1_tap_position(int tap_pos) { int block; int i; int offset; int wcr_val; offset= 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); else if (block <= 3) { switch(block) { case (0): return ((unsigned)tap_pos) ; case (1): { wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); } case (2): { wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned)--wcr_val); } case (3): { wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); } } } return((unsigned)01100000); } x9523
27 fn8209.0 march 10, 2005 appendix 2 dcp1 (100 tap) tap position to data byte translation algorithm example. (example 2) unsigned dcp100_tap_position(int tap_pos) { /* optional range checking */ if (tap_pos < 0) return ((unsigned)0); /* set to min val */ else if (tap_pos >99) return ((unsigned) 96); /* set to max val */ /* 100 tap dcp encoding formula */ if (tap_pos > 74) return ((unsigned) (195 - tap_pos)); else if (tap_pos > 49) return ((unsigned) (14 + tap_pos)); else if (tap_pos > 24) return ((unsigned) (81 - tap_pos)); else return (tap_pos); } x9523
28 fn8209.0 march 10, 2005 20 ball bga (x9523) a b a d c e 1234 b a d c e 1 2 3 4 b top view (bump side down) side view (bump side down) bottom view (bump side up) c d e f k a j b note: drawing not to scale = die orientation mark symbol millimeters inches min nom max min nom max package body dimension x a 2.524 2.554 2.584 0.09938 0.10056 0.10174 package body dimension y b 3.794 3.824 3.854 0.14938 0.15056 0.15174 package height c 0.654 0.682 0.710 0.02575 0.02685 0.02795 body thickness d 0.444 0.457 0.470 0.01748 0.01799 0.01850 ball height e 0.210 0.225 0.240 0.00827 0.00886 0.00945 ball diameter f 0.316 0.326 0.336 0.01244 0.01283 0.01323 ball pitch ? x axis j 0.5 0.01969 ball pitch ? y axis k 0.5 0.01969 ball to edge spacing ? distance along x l 0.497 0.527 0.557 0.01957 0.02075 0.02193 ball to edge spacing ? distance along y m 0.882 0.912 0.942 0.03473 0.03591 0.03709 l m ball matrix 4321 a rl2 rw2 v1/vcc v2ro b v3 rh2 v1ro v2 c wp v3ro nc nc d scl mr nc rh1 e sda rl1 rw1 vss x9523
29 fn8209.0 march 10, 2005 note: all dimensions in inches (in parentheses in millimeters) 20-lead plastic, tssop package type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .252 (6.4) .260 (6.6) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ?a? .031 (.80) .041 (1.05) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical x9523
30 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8209.0 march 10, 2005 ordering information device preset (factory shipped) v tripx threshold levels (x = 1,2,3) a = optimized for 3.3v system monitoring ? b = optimized for 5v system monitoring ? temperature range i = industrial -40 c to +85 c package v20 = 20-lead tssop b20 = 20-lead xbga x9523 p t xbga part mark convention 20 lead xbga top mark x9523b20i-a xaco X9523B20I-B xacs - y ? for details of preset threshold values , see "d.c. operating characteristics" x9523

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